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Lattice Semiconductor
Figure 7. PI40 Egress Cell Structure (FOPI Format 1)
CSIX-to-PI40 IP Core User’s Guide
PI40 Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
2
3
4
5
6
7
RES
BKPQ1[3:0]
BKPQ3[3:0]
PBKP[3:0]
BKPQ1[11:4]
BKPQ2[7:0]
BKPQ3[11:4]
BKPQ4[7:0]
BKPQ5[11:4]
CELLTYPE[2:0]
BKPQ2[11:8]
BKPQ4[11:8]
8
BKPQ5[3:0]
BKP1SC
BKP1ON
BKP2SC
BKP2ON
9
BKP3SC
BKP3ON
BKP4SC
BKP4ON
BKP5SC
BKP5ON
MCBKP[1:0]
10
11
12
13
14
15
16
17 to (N+16)
N+17
N+18
(N+19) to
74, 82 or 90
75, 83 or 91
DIAG[7:0]
CSIX Base Header
CSIX Base Header
CSIX Extension Header
CSIX Extension Header
CSIX Extension Header
CSIX Extension Header
CSIX Payload (N bytes, where N ≤ MAX_FRAME_PAYLOAD_SIZE)
CSIX Vertical Parity
CSIX Vertical Parity
Remaining PI40 Payload (pad if needed)
BIP8
PI40 Cells from ORSO Embedded Core
Egress direction PI40 cell reception is managed by the ORSO 2-link Input Port Controller (IPC2). The IPC2 man-
ages cell reception on the corresponding SERDES links, automatically extracting the cells and checking BIP8. Valid
cells are passed to the IP core EFI block. The IPC2 indicates when a cell is available by asserting the CELLSTART
signal. It also provides BIP_ERR and CELLDROP indications. Complete details on the IPC2 interface and function-
ality are given in the ORCA ORSO82G5 data sheet.
Egress PI40 Cell Processing
The EFI extracts switch header information from all valid egress cells and passes it to the Back Pressure Processor
(BPP). The switch header CELLTYPE ?eld is examined and all cells other than Unicast or Multicast ID are dis-
carded. Unicast and Multicast ID Cframes are extracted from the cell payload, using the Cframe payload length
information in the CSIX Base Header to determine the valid Cframe data in the cell payload. Any remaining PI40
payload pad is discarded. The Unicast and Multicast ID Cframes are then written to the CSIX Outbound Data FIFO.
Backpressure Processing
Every PI40 FOPI Format 1 cell header contains Port Backpressure (PBKP) and Multicast Backpressure (MCBKP)
information and Queue Backpressure information for ?ve different queues as shown in Figure 7. The information is
passed to the BPP block, where it is processed and used to generate CSIX Flow Control Cframes that are written
to the CSIX Outbound Control FIFO. The CSIX Flow Control Cframe format is shown in Figure 8. Entries 1 through
5 contain ?ow control information about the 5 queues detailed in the PI40 FOPI Format 1 cell header. Entry 6 con-
tains ?ow control information for low priority Multicast and entry 7 contains ?ow control information for high priority
Multicast.
10
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